View M58CR064-ZBT_2153815.PDF datasheet online --- IC-ON-LINE

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1/70 june 2003 m58cr064c, m58cr064d m58cr064p, m58cr064q 64 mbit (4mb x 16, dual bank, burst ) 1.8v supply flash memory features summary n supply voltage Cv dd = 1.65v to 2v for program, erase and read Cv ddq = 1.65v to 3.3v for i/o buffers Cv pp = 12v for fast program (optional) n synchronous / asynchronous read C synchronous burst read mode : 54mhz C asynchronous/ synchronous page read mode C random access: 85, 90, 100, 120ns n programming time C 10s by word typical C double/quadruple word program option n memory blocks C dual bank memory array: 16/48 mbit C parameter blocks (top or bottom location) n dual operations C program erase in one bank while read in other C no delay between read and write operations n block locking C all blocks locked at power up C any combination of blocks can be locked Cwp for block lock-down n security C 128 bit user programmable otp cells C 64 bit unique device number C one parameter block permanently lockable n common flash interface (cfi) n 100,000 program/erase cycles per block figure 1. package n electronic signature C manufacturer code: 20h C top device code, m58cr064c: 88cah C bottom device code, m58cr064d: 88cbh C top device code, m58cr064p: 8801h C bottom device code, m58cr064q: 8802h fbga tfbga56 (zb) 6.5 x 10mm
m58cr064c, m58cr064d, m58cr064p, m58cr064q 2/70 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 address inputs (a0-a21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 data input/output (dq0-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 chip enable (e). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 output enable (g). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 write enable (w). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 write protect (wp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 reset/power-down (rp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 latch enable (l). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 clock (k).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 wait (wait). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 v ddq supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 v pp program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 v ss ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 v ssq ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 bus write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 address latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 command interface - standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 read array command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 read status register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 read cfi query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 clear status register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 protection register program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 set configuration register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 block lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 block unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 block lock-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 5. standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. security block and protection register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 command interface - factory program commands . . . . . . . . . . . . . . . . . . . . . . . . . 18 bank erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 double word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 quadruple word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7. factory program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 program/erase controller status bit (sr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 erase suspend status bit (sr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 erase status bit (sr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 program status bit (sr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 v pp status bit (sr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 program suspend status bit (sr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 block protection status bit (sr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 reserved bit (sr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 read select bit (cr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 x-latency bits (cr13-cr11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 power-down bit (cr10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 wait configuration bit (cr8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 burst type bit (cr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 valid clock edge bit (cr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 wrap burst bit (cr3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 burst length bits (cr2-cr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9. configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 6. x-latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 7. wait configuration example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 read modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 asynchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 synchronous burst read mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 single synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
m58cr064c, m58cr064d, m58cr064p, m58cr064q 4/70 dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 11. dual operations allowed in other bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 12. dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 block locking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 reading a blocks lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 locking operations during erase suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13. lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 program and erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 14. program, erase times and program, erase endurance cycles . . . . . . . . . . . . . . . . . . . 30 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 15. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 16. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 8. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 9. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 table 17. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 18. dc characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 19. dc characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 10. asynchronous random access read ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 11. asynchronous page read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 20. asynchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 12. synchronous burst read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 13. single synchronous read ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 21. synchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 14. write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 22. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 15. write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 23. write ac characteristics, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 16. reset and power-up ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 24. reset and power-up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 17. tfbga56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, bottom view package outline. . 46 table 25. tfbga56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, package mechanical data . . . . . 46 figure 18. tfbga56 daisy chain - package connections (top view through package) . . . . . . . . 47 figure 19. tfbga56 daisy chain - pcb connection proposal (top view through package). . . . . 48 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 26. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9
5/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q table 27. daisy chain ordering scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 appendix a. block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 28. top boot block addresses, m58cr064c, m58cr064p . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 29. bottom boot block addresses, m58cr064d, m58cr064q . . . . . . . . . . . . . . . . . . . . . . 52 appendix b. common flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 30. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 31. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 32. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 33. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 34. primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 35. burst read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 appendix c. flowcharts and pseudo codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 20. program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 21. double word program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 22. quadruple word program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 23. program suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . 61 figure 24. block erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 25. erase suspend & resume flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . 63 figure 26. locking operations flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 27. protection register program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . 65 appendix d. command interface state tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 36. command interface states - lock table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 37. command interface states - modify table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 38. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
m58cr064c, m58cr064d, m58cr064p, m58cr064q 6/70 summary description the m58cr064 is a 64 mbit (4mbit x16) non-vola- tile flash memory that may be erased electrically at block level and programmed in-system on a word-by-word basis using a 1.65v to 2v v dd sup- ply for the circuitry and a 1.65v to 3.3v v ddq sup- ply for the input/output pins. an optional 12v v pp power supply is provided to speed up customer programming. in m58cr064c and m58cr064d the v pp pin can also be used as a control pin to provide absolute protection against program or erase. in m58cr064p and m58cr064q this fea- ture is disabled. the device features an asymmetrical block archi- tecture. m58cr064 has an array of 135 blocks, and is divided into two banks, banks a and b. the dual bank architecture allows dual operations, while programming or erasing in one bank, read operations are possible in the other bank. only one bank at a time is allowed to be in program or erase mode. it is possible to perform burst reads that cross bank boundaries. the bank architecture is summarized in table 2, and the memory maps are shown in figure 4. the parameter blocks are located at the top of the memory address space for the m58cr064c and m58cr064p, and at the bot- tom for the m58cr064d and m58cr064q. each block can be erased separately. erase can be suspended, in order to perform program in any other block, and then resumed. program can be suspended to read data in any other block and then resumed. each block can be programmed and erased over 100,000 cycles using the supply voltage v dd . program and erase commands are written to the command interface of the memory. an internal program/erase controller takes care of the tim- ings necessary for program and erase operations. the end of a program or erase operation can be detected and any error conditions identified in the status register. the command set required to control the memory is consistent with jedec stan- dards. the device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. in synchronous burst mode, data is output on each clock cycle at frequencies of up to 54mhz. the m58cr064 features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling in- stant code and data protection. all blocks have three levels of protection. they can be locked and locked-down individually preventing any acciden- tal programming or erasure. in m58cr064c and m58cr064d there is an additional hardware pro- tection against program and erase. when v pp v pplk all blocks are protected against program or erase. all blocks are locked at power- up. the device includes a protection register and a security block to increase the protection of a sys- tems design. the protection register is divided into two segments: a 64 bit segment containing a unique device number written by st, and a 128 bit segment one-time-programmable (otp) by the user. the user programmable segment can be permanently protected. the security block, pa- rameter block 0, can be permanently protected by the user. figure 5, shows the security block and protection register memory map. the memory is offered in a tfbga56, 6.5 x 10mm, 0.75 mm ball pitch package and is supplied with all the bits erased (set to 1).
7/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q figure 2. logic diagram table 1. signal names ai90000 22 a0-a21 w dq0-dq15 v dd m58cr064c m58cr064d m58cr064p m58cr064q e v ss 16 g rp wp v ddq v pp l k wait v ssq a0-a21 address inputs dq0-dq15 data input/outputs, command inputs e chip enable g output enable w write enable rp reset/power-down wp write protect kclock l latch enable wait wait v dd supply voltage v ddq supply voltage for input/output buffers v pp optional supply voltage for fast program & erase v ss ground v ssq ground input/output supply nc not connected internally
m58cr064c, m58cr064d, m58cr064p, m58cr064q 8/70 figure 3. tfbga connections (top view through package) table 2. bank architecture bank size parameter blocks main blocks bank a 16 mbit 8 blocks of 4 kword 31 blocks of 32 kword bank b 48 mbit - 96 blocks of 32 kword ai90001 dq1 dq13 dq3 dq12 dq6 dq8 d a1 a3 a6 a9 a12 a15 c a2 a5 a17 a18 a10 b a4 a7 a19 v pp a8 a11 a13 a 8 7 6 5 4 3 2 1 a20 g f e v ss v dd k rp l w a14 wait a16 wp v ddq dq4 dq2 e a0 v ss dq15 dq14 dq11 dq10 dq9 dq0 g dq7 v ssq dq5 v dd v ddq v ssq a21 nc
9/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q figure 4. memory map ai90002 512 kbit or 32 kword 000000h 007fffh 512 kbit or 32 kword 3f0000h 3f7fffh top boot block address lines a21-a0 512 kbit or 32 kword 2f8000h 2fffffh total of 96 main blocks (bottom bank) 512 kbit or 32 kword 300000h 307fffh 64 kbit or 4 kword 3ff000h 3fffffh 64 kbit or 4 kword 3f8000h 3f8fffh total of 31 main blocks (top bank) total of 8 parameter blocks (top bank) bank b bank a 64 kbit or 4 kword 000000h 000fffh 512 kbit or 32 kword 0f8000h 0fffffh bottom boot block address lines a21-a0 64 kbit or 4 kword 007000h 007fffh total of 8 parameter blocks (bottom bank) 512 kbit or 32 kword 008000h 00ffffh 512 kbit or 32 kword 3f8000h 3fffffh 512 kbit or 32 kword 100000h 107fffh total of 31 main blocks (bottom bank) total of 96 main blocks (top bank) bank b bank a
m58cr064c, m58cr064d, m58cr064p, m58cr064q 10/70 signal descriptions see figure 2 logic diagram and table 1,signal names, for a brief overview of the signals connect- ed to this device. address inputs (a0-a21). the address inputs select the cells in the memory array to access dur- ing bus read operations. during bus write opera- tions they control the commands sent to the command interface of the internal state machine. data input/output (dq0-dq15). the data i/o outputs the data stored at the selected address during a bus read operation or inputs a command or the data to be programmed during a bus write operation. chip enable (e ). the chip enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. when chip enable is at v il and reset/power-down is at v ih the device is in active mode. when chip enable is at v ih the memory is deselected, the outputs are high imped- ance and the power consumption is reduced to the stand-by level. output enable (g ). the output enable controls the outputs during the bus read operation of the memory. write enable (w ). the write enable controls the bus write operation of the memorys command interface. the data and address inputs are latched on the rising edge of chip enable or write enable whichever occurs first. write protect (wp ). write protect is an input that gives an additional hardware protection for each block. when write protect is at v il , the lock- down is enabled and the protection status of the locked-down blocks cannot be changed. when write protect is at v ih , the lock-down is disabled and the locked-down blocks can be locked or un- locked. (refer to table 13, lock status). reset/power-down (rp ). the reset/power- down input provides a hardware reset of the mem- ory, and/or power-down functions, depending on the configuration register status. when reset/ power-down is at v il , the memory is in reset mode: the outputs are high impedance and if the power-down function is enabled the current con- sumption is reduced to the reset supply current i dd2 . refer to table 18, dc characteristics - cur- rents for the value of i dd2. after reset all blocks are in the locked state and the configuration reg- ister is reset. when reset/power-down is at v ih , the device is in normal operation. exiting reset mode the device enters asynchronous read mode, but a negative transition of chip enable or latch enable is required to ensure valid data outputs. the reset/power-down pin can be interfaced with 3v logic without any additional circuitry. it can be tied to v rph (refer to table 19, dc characteris- tics). latch enable (l ). latch enable latches the ad- dress bits on its rising edge. the address latch is transparent when latch enable is at v il and it is in- hibited when latch enable is at v ih . latch enable can be kept low (also at board level) when the latch enable function is not required or supported. clock (k). the clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a clock edge (rising or falling, according to the configura- tion settings) when latch enable is at v il . clock is don't care during asynchronous read and in write operations. wait (wait ). wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. this output is high imped- ance when chip enable or output enable are at v ih or reset/power-down is at v il . it can be con- figured to be active during the wait cycle or one clock cycle in advance. v dd supply voltage. v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). v ddq supply voltage. v ddq provides the power supply to the i/o pins and enables all outputs to be powered independently from v dd . v ddq can be tied to v dd or can use a separate supply. v pp program supply voltage. v pp is both a control input and a power supply pin. in m58cr064c/d the two functions are selected by the voltage range applied to the pin. in the m58cr064p/q the control feature is disabled. in m58cr064c/d if v pp is kept in a low voltage range (0v to v ddq ) v pp is seen as a control input. in this case a voltage lower than v pplk gives an absolute protection against program or erase, while v pp > v pp1 enables these functions (see ta- bles 18 and 19, dc characteristics for the relevant values). v pp is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. if v pp is in the range of v pph it acts as a power supply pin. in this condition v pp must be stable un- til the program/erase algorithm is completed. v ss ground. v ss ground is the reference for the core supply. it must be connected to the system ground. v ssq ground. v ssq ground is the reference for the input/output circuitry driven by v ddq . v ssq must be connected to v ss
11/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q note: each device in a system should have v dd , v ddq and v pp decoupled with a 0.1f ce- ramic capacitor close to the pin (high frequen- cy, inherently low inductance capacitors should be as close as possible to the pack- age). see figure 9, ac measurement load cir- cuit. the pcb track widths should be sufficient to carry the required v pp program and erase currents. bus operations there are six standard bus operations that control the device. these are bus read, bus write, ad- dress latch, output disable, standby and reset. see table 3, bus operations, for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus write operations. bus read. bus read operations are used to out- put the contents of the memory array, the elec- tronic signature, the status register and the common flash interface. both chip enable and output enable must be at v il in order to perform a read operation. the chip enable input should be used to enable the device. output enable should be used to gate data onto the output. the data read depends on the previous command written to the memory (see command interface section). refer to the read ac waveform figures and char- acteristics tables in the dc and ac parameters section for details of when the output becomes val- id. bus write. bus write operations write com- mands to the memory or latch input data to be programmed. a bus write operation is initiated when chip enable and write enable are at v il with output enable at v ih . commands, input data and addresses are latched on the rising edge of write enable or chip enable, whichever occurs first. the addresses can also be latched prior to the write operation by toggling latch enable. in this case the latch enable should be tied to v ih during the bus write operation. see figures 14 and 15, write ac waveforms, and tables 22 and 23, write ac characteristics, for details of the timing requirements. address latch. address latch operations input valid addresses. both chip enable and latch en- able must be at v il during address latch opera- tions. the addresses are latched on the rising edge of latch enable. output disable. the outputs are high imped- ance when the output enable is at v ih . standby. standby disables most of the internal circuitry allowing a substantial reduction of the cur- rent consumption. the memory is in stand-by when chip enable and reset/power-down are at v ih . the power consumption is reduced to the stand-by level and the outputs are set to high im- pedance, independently from the output enable or write enable inputs. if chip enable switches to v ih during a program or erase operation, the de- vice enters standby mode when finished. reset. during reset mode the memory is dese- lected and the outputs are high impedance. the memory is in reset mode when reset/power- down is at v il . the power consumption is reduced to the standby level, independently from the chip enable, output enable or write enable inputs. if reset is pulled to v ss during a program or erase, this operation is aborted and the memory content is no longer valid. table 3. bus operations note: 1. x = don't care. 2. l can be tied to v ih if the valid address has been previously latched. 3. depends on g . operation e g w l rp wait dq15-dq0 bus read v il v il v ih v il (2) v ih data output bus write v il v ih v il v il (2) v ih hi-z data input address latch v il x v ih v il v ih data output or hi-z (3) output disable v il v ih v ih x v ih hi-z hi-z standby v ih xxx v ih hi-z hi-z reset x x x x v il hi-z hi-z
m58cr064c, m58cr064d, m58cr064p, m58cr064q 12/70 command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. an internal program/erase controller han- dles all timings and verifies the correct execution of the program and erase commands. the pro- gram/erase controller provides a status register whose output may be read at any time to monitor the progress or the result of the operation. the command interface is reset to read mode when power is first applied, when exiting from re- set or whenever v dd is lower than v lko . com- mand sequences must be followed exactly. any invalid combination of commands will reset the de- vice to read mode. refer to table 4, command codes and appendix d, tables 36 and 37, command interface states - modify and lock tables, for a summary of the command interface. the command interface is split into two types of commands: standard commands and factory program commands. the following sections ex- plain in detail how to perform each command. table 4. command codes hex code command 01h block lock confirm 03h set configuration register confirm 10h alternative program setup 20h block erase setup 2fh block lock-down confirm 30h double word program setup 40h program setup 50h clear status register 55h quadruple word program setup 60h block lock setup, block unlock setup, block lock down setup and set configuration register setup 70h read status register 80h bank erase setup 90h read electronic signature 98h read cfi query b0h program/erase suspend c0h protection register program d0h program/erase resume, block erase confirm, bank erase confirm, block unlock confirm ffh read array
13/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q command interface - standard commands the following commands are the basic commands used to read, write to and configure the device. refer to table 5, standard commands, in con- junction with the following text descriptions. read array command the read array command returns the addressed bank to read array mode. one bus write cycle is required to issue the read array command and re- turn the addressed bank to read array mode. subsequent read operations will read the ad- dressed location and output the data. a read ar- ray command can be issued in one bank while programming or erasing in the other bank. howev- er if a read array command is issued to a bank currently executing a program or erase operation the command will be ignored. read status register command a banks status register indicates when a pro- gram or erase operation is complete and the suc- cess or failure of operation itself. issue a read status register command to read the status reg- ister content of the addressed bank. the read status register command can be issued at any time, even during program or erase operations. the following bus read operations output the con- tent of the status register of the addressed bank. the status register is latched on the falling edge of e or g signals, and can be read until e or g re- turns to v ih . either e or g must be toggled to up- date the latched data. see table 8 for the description of the status register bits. this mode supports asynchronous or single synchronous reads only. read electronic signature command the read electronic signature command reads the manufacturer and device codes, the block locking status, the protection register, and the configuration register. the read electronic signature command consists of one write cycle to an address within the bottom bank. a subsequent read operation in the address of the bottom bank will output the manufacturer code, the device code, the protection status of blocks of the bottom bank, the die revision code, the protection register, or the read configuration register (see table 6). if the first write cycle of read electronic signature command is issued to an address within the top bank, a subsequent read operation in an address of the top bank will output the protection status of blocks of the top bank. the status of the other bank is not affected by the command (see table 11). this mode supports asynchronous or single synchronous reads only, it does not support page mode or synchronous burst reads. read cfi query command the read cfi query command is used to read data from the common flash interface (cfi) memory area located in the bottom bank. the read cfi query command consists of one bus write cycle, to an address within the bottom bank. once the command is issued subsequent bus read operations in the same bank read from the common flash interface. if a read cfi query command is issued in a bank that is executing a program or erase operation the bank will go into read status register mode, sub- sequent bus read cycles w ill output the status register and the program/erase controller will continue to program or erase in the background. when the program or erase operation has fin- ished the device will enter read cfi query mode. this mode supports asynchronous or single syn- chronous reads only, it does not support page mode or synchronous burst reads. the status of the other banks is not affected by the command (see table 11). after issuing a read cfi query command, a read array command should be issued to the addressed bank to return the bank to read mode. see appendix b, common flash interface, tables 30, 31, 32, 33, 34 and 35 for details on the infor- mation contained in the common flash interface memory area. clear status register command the clear status register command can be used to reset (set to 0) error bits sr1, sr3, sr4 and sr5 in the status register of the addressed bank. one bus write cycle is required to issue the clear status register command. after the clear status register command the bank returns to read array mode. the error bits in the status register do not auto- matically return to 0 when a new command is is- sued. the error bits in the status register should be cleared before attempting a new program or erase command. block erase command the block erase command can be used to erase a block. it sets all the bits within the selected block to 1. all previous data in the block is lost. if the block is protected then the erase operation will abort, the data in the block will not be changed and the status register will output the error. the block erase command can be issued at any moment, re- gardless of whether the block has been pro- grammed or not. two bus write cycles are required to issue the command. n the first bus cycle sets up the erase command.
m58cr064c, m58cr064d, m58cr064p, m58cr064q 14/70 n the second latches the block address in the internal state machine and starts the program/ erase controller. if the second bus cycle is not write erase confirm (d0h), status register bits sr4 and sr5 are set and the command aborts. erase aborts if reset turns to v il . as data integrity cannot be guaran- teed when the erase operation is aborted, the block must be erased again. once the command is issued the device outputs the status register data when any address within the bank is read. at the end of the operation the bank will remain in read status register mode un- til a read array, read cfi query or read elec- tronic signature command is issued. during erase operations the bank containing the block being erased will only accept the read sta- tus register and the program/erase suspend command, all other commands will be ignored. refer to dual operations section for detailed infor- mation about simultaneous operations allowed in banks not being erased. typical erase times are given in table 14, program, erase times and pro- gram/erase endurance cycles. see appendix c, figure 24, block erase flow- chart and pseudo code, for a suggested flowchart for using the block erase command. program command the memory array can be programmed word-by- word. only one word in one bank can be pro- grammed at any one time. two bus write cycles are required to issue the program command. n the first bus cycle sets up the program command. n the second latches the address and the data to be written and starts the program/erase controller. after programming has started, read operations in the bank being programmed output the status register content. during program operations the bank being pro- grammed will only accept the read status regis- ter and the program/erase suspend command. refer to dual operations section for detailed infor- mation about simultaneous operations allowed in banks not being programmed. typical program times are given in table 14, program, erase times and program/erase endurance cycles. programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the memory location must be reprogrammed. see appendix c, figure 20, program flowchart and pseudo code, for the flowchart for using the program command. program/erase suspend command the program/erase suspend command is used to pause a program or block erase operation. a bank erase operation cannot be suspended. one bus write cycle is required to issue the pro- gram/erase suspend command. once the pro- gram/erase controller has paused bits sr7, sr6 and/ or sr 2 of the status register will be set to 1. the command must be addressed to the bank containing the program or erase operation. during program/erase suspend the command in- terface will accept the program/erase resume, read array (cannot read the suspended block), read status register, read electronic signature and read cfi query commands. additionally, if the suspend operation was erase then the clear status register, program, block lock, block lock- down or protection program commands will also be accepted. the block being erased may be pro- tected by issuing the block lock, block lock- down or protection register program commands. only the blocks not being erased may be read or programmed correctly. when the program/erase resume command is issued the operation will complete. refer to the dual operations section for detailed information about simultaneous opera- tions allowed during program/erase suspend. during a program/erase suspend, the device can be placed in standby mode by taking chip enable to v ih . program/erase is aborted if reset turns to v il . see appendix c, figure 23, program suspend & resume flowchart and pseudo code, and figure 25, erase suspend & resume flowchart and pseudo code for flowcharts for using the program/ erase suspend command. program/erase resume command the program/erase resume command can be used to restart the program/erase controller after a program/erase suspend command has paused it. one bus write cycle is required to issue the command. the command must be written to the bank containing the program or erase suspend. the program/erase resume command changes the read mode of the target bank to read status register mode. if a program command is issued during a block erase suspend, then the erase cannot be re- sumed until the programming operation has com- pleted. it is possible to accumulate suspend operations. for example: suspend an erase oper- ation, start a programming operation, suspend the programming operation then read the array. see appendix c, figure 23, program suspend & re- sume flowchart and pseudo code, and figure 25, erase suspend & resume flowchart and pseudo
15/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q code for flowcharts for using the program/erase resume command. protection register program command the protection register program command is used to program the 128 bit user one-time-pro- grammable (otp) segment of the protection reg- ister. the segment is programmed 16 bits at a time. when shipped all bits in the segment are set to 1. the user can only program the bits to 0. two write cycles are required to issue the protec- tion register program command. n the first bus cycle sets up the protection register program command. n the second latches the address and the data to be written to the protection register and starts the program/erase controller. read operations output the status register con- tent after the programming has started. the segment can be protected by programming bit 1 of the protection lock register. bit 1 of the pro- tection lock register also protects bit 2 of the pro- tection lock register. programming bit 2 of the protection lock register will result in a permanent protection of parameter block #0 (see figure 5, security block and protection register memory map). attempting to program a previously protect- ed protection register will result in a status reg- ister error. the protection of the protection register and/or the security block is not revers- ible. the protection register program cannot be sus- pended. see appendix c, figure 27, protection register program flowchart and pseudo code, for a flowchart for using the protection register program command. set configuration register command. the set configuration register command is used to write a new value to the configuration control register which defines the burst length, type, x la- tency, synchronous/asynchronous read mode and the valid clock edge configuration. two bus write cycles are required to issue the set configuration register command. n the first cycle writes the setup command and the address corresponding to the configuration register content. n the second cycle writes the configuration register data and the confirm command. once the command is issued the memory returns to read mode. the value for the configuration register is always presented on a0-a15. cr0 is on a0, cr1 on a1, etc.; the other address bits are ignored. block lock command the block lock command is used to lock a block and prevent program or erase operations from changing the data in it. all blocks are locked at power-up or reset. two bus write cycles are required to issue the block lock command. n the first bus cycle sets up the block lock command. n the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. table. 13 shows the lock status after issuing a block lock command. the block lock bits are volatile, once set they re- main set until a hardware reset or power-down/ power-up. they are cleared by a block unlock command. refer to the section, block locking, for a detailed explanation. see appendix c, figure 26, locking operations flowchart and pseudo code, for a flowchart for using the lock command. block unlock command the block unlock command is used to unlock a block, allowing the block to be programmed or erased. two bus write cycles are required to is- sue the block unlock command. n the first bus cycle sets up the block unlock command. n the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. table 13 shows the protection status after issuing a block unlock command. refer to the section, block locking, for a detailed explanation and ap- pendix c, figure 26, locking operations flow- chart and pseudo code, for a flowchart for using the unlock command. block lock-down command a locked or unlocked block can be locked-down by issuing the block lock-down command. a locked- down block cannot be programmed or erased, or have its protection status changed when wp is low, v il . when wp is high, v ih, the lock-down function is disabled and the locked blocks can be individually unlocked by the block unlock com- mand. two bus write cycles are required to issue the block lock-down command. n the first bus cycle sets up the block lock command. n the second bus write cycle latches the block address.
m58cr064c, m58cr064d, m58cr064p, m58cr064q 16/70 the lock status can be monitored for each block using the read electronic signature command. locked-down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. table. 13 shows the lock status af- ter issuing a block lock-down command. refer to the section, block locking, for a detailed explana- tion and appendix c, figure 26, locking opera- tions flowchart and pseudo code, for a flowchart for using the lock-down command. table 5. standard commands note: 1. x = don't care, wa=word address in targeted bank, rd=read data, srd=status register data, esd=electronic signature data, qd=query data, ba=block address, bka= bank address, bbka= bottom bank address, pd=program data, pra=protection register address, prd=protection register data, crd=configuration register data. 2. must be same bank as in the first cycle. the signature addresses are listed in table 6. 3. when addressed to a block in the top bank, reads block protection data only. commands cycles bus operations 1st cycle 2nd cycle op. add data op. add data read array 1+ write bka ffh read wa rd read status register 1+ write bka 70h read bka (2) srd read electronic signature 1+ write bbka or bka (3) 90h read bbka or bka (2,3) esd (3) read cfi query 1+ write bbka 98h read bbka (2) qd clear status register 1 write bka 50h block erase 2 write bka 20h write ba d0h program 2 write bka 40h or 10h write wa pd program/erase suspend 1 write bka b0h program/erase resume 1 write bka d0h protection register program 2 write pra c0h write pra prd set configuration register 2 write crd 60h write crd 03h block lock 2 write bka 60h write ba 01h block unlock 2 write bka 60h write ba d0h block lock-down 2 write bka 60h write ba 2fh
17/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q table 6. electronic signature codes note: cr=configuration register. figure 5. security block and protection register memory map code address (h) data (h) manufacturer code bottom bank address + 00 0020 device code top (m58cr064c) bottom bank address + 01 88ca bottom (m58cr064d) 88cb top (m58cr064p) 8801 bottom (m58cr064q) 8802 block protection lock block address + 02 0001 unlocked 0000 locked and locked-down 0003 unlocked and locked-down 0002 reserved bottom bank address + 03 reserved configuration register bottom bank address + 05 cr protection register lock st factory default bottom bank address + 80 xx06 security block permanently locked xx02 otp area permanently locked xx04 security block and otp area permanently locked xx00 protection register bottom bank address + 81 bottom bank address + 84 unique device number bottom bank address + 85 bottom bank address + 8c otp area ai06181 parameter block # 0 user programmable otp unique device number protection register lock 2 1 0 8ch 85h 84h 81h 80h protection register security block
m58cr064c, m58cr064d, m58cr064p, m58cr064q 18/70 command interface - factory program commands the factory program commands are used to speed up programming. they require v pp to be at v pph except for the bank erase command which also operates at v pp = v dd . refer to table 7, fac- tory program commands, in conjunction with the following text descriptions. bank erase command the bank erase command can be used to erase a bank. it sets all the bits within the selected bank to 1. all previous data in the bank is lost. the bank erase command will ignore any protected blocks within the bank. if all blocks in the bank are pro- tected then the bank erase operation will abort and the data in the bank will not be changed. the status register will not output any error. bank erase operations can be performed at both v pp = v pph and v pp = v dd . two bus write cycles are required to issue the command. n the first bus cycle sets up the bank erase command. n the second latches the bank address in the internal state machine and starts the program/ erase controller. if the second bus cycle is not write bank erase confirm (d0h), status register bits sr4 and sr5 are set and the command aborts. erase aborts if reset turns to v il . as data integrity cannot be guaranteed when the erase operation is aborted, the bank must be erased again. once the command is issued the device outputs the status register data when any address within the bank is read. at the end of the operation the bank will remain in read status register mode un- til a read array, read cfi query or read elec- tronic signature command is issued. during bank erase operations the bank being erased will only accept the read status register command, all other commands will be ignored. a bank erase operation cannot be suspended. for optimum performance, bank erase com- mands should be limited to a maximum of 100 pro- gram/erase cycles per block. after 100 program/ erase cycles the internal algorithm will still operate properly but some degradation in performance may occur. dual operations are not supported during bank erase operations and the command cannot be suspended. typical erase times are given in table 14, pro- gram, erase times and program/erase endur- ance cycles. double word program command the double word program command improves the programming throughput by writing a page of two adjacent words in parallel. the two words must differ only for the address a0. programming should not be attempted when v pp is not at v pph . the command can be executed if v pp is below v pph but the result is not guaranteed. three bus write cycles are necessary to issue the double word program command. n the first bus cycle sets up the double word program command. n the second bus cycle latches the address and the data of the first word to be written. n the third bus cycle latches the address and the data of the second word to be written and starts the program/erase controller. read operations in the bank being programmed output the status register content after the pro- gramming has started. during double word program operations the bank being programmed will only accept the read sta- tus register command, all other commands will be ignored. dual operations are not supported during double word program operations. it is not recom- mended to suspend the double word program command. typical program times are given in ta- ble 14, program, erase times and program/erase endurance cycles. programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. see appendix c, figure 21, double word pro- gram flowchart and pseudo code, for the flow- chart for using the double word program command. quadruple word program command the quadruple word program command im- proves the programming throughput by writing a page of four adjacent words in parallel. the four words must differ only for the addresses a0 and a1. programming should not be attempted when v pp is not at v pph . the command can be executed if v pp is below v pph but the result is not guaranteed. five bus write cycles are necessary to issue the quadruple word program command. n the first bus cycle sets up the double word program command. n the second bus cycle latches the address and the data of the first word to be written.
19/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q n the third bus cycle latches the address and the data of the second word to be written. n the fourth bus cycle latches the address and the data of the third word to be written. n the fifth bus cycle latches the address and the data of the fourth word to be written and starts the program/erase controller. read operations to the bank being programmed output the status register content after the pro- gramming has started. programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. during quadruple word program operations the bank being programmed will only accept the read status register command, all other commands will be ignored. dual operations are not supported during quadru- ple word program operations. it is not recom- mended to suspend the quadruple word program command. typical program times are given in ta- ble 14, program, erase times and program/erase endurance cycles. see appendix c, figure 22, quadruple word pro- gram flowchart and pseudo code, for the flow- chart for using the quadruple word program command. table 7. factory program commands note: 1. wa=word address in targeted bank, bka= bank address, pd=program data, wa1 is the start address. 2. word addresses 1 and 2 must be consecutive addresses differing only for a0. 3. word addresses 1,2,3 and 4 must be consecutive addresses differing only for a0 and a1. command phase cycles bus write operations 1st 2nd 3rd 4th 5th add data add data add data add data add data bank erase 2 bka 80h bka d0h double word program (2) 3 bka 30h wa1 pd1 wa2 pd2 quadruple word program (3) 5 bka 55h wa1 pd1 wa2 pd2 wa3 pd3 wa4 pd4
m58cr064c, m58cr064d, m58cr064p, m58cr064q 20/70 status register the m58cr064 has two status registers, one for each bank. the status registers provide informa- tion on the current or previous program or erase operations executed in each bank. issue a read status register command to read the contents of the status register, refer to read status register command section for more details. to output the contents, the status register is latched and updat- ed on the falling edge of the chip enable or output enable signals, and can be read until chip enable or output enable returns to v ih . the status reg- ister can only be read using single asynchronous or single synchronous reads. bus read opera- tions from any address within the bank, always read the status register during program and erase operations. the various bits convey information about the sta- tus and any errors of the operation. bits sr7, sr6 and sr2 give information on the status of the bank and are set and reset by the device. bits sr5, sr4, sr3 and sr1 give information on errors, they are set by the device but must be reset by is- suing a clear status register command or a hard- ware reset. if an error bit is set to 1 the status register should be reset before issuing another command. the bits in the status register are summarized in table 8, status register bits. refer to table 8 in conjunction with the following text descriptions. program/erase controller status bit (sr7). the program/erase controller status bit indicates whether the program/erase controller is active or inactive in the addressed bank. when the pro- gram/erase controller status bit is low (set to 0), the program/erase controller is active; when the bit is high (set to 1), the program/erase control- ler is inactive, and the device is ready to process a new command. the program/erase controller status is low im- mediately after a program/erase suspend com- mand is issued until the program/erase controller pauses. after the program/erase controller paus- es the bit is high. during program, erase, operations the program/ erase controller status bit can be polled to find the end of the operation. other bits in the status reg- ister should not be tested until the program/erase controller completes the operation and the bit is high. after the program/erase controller completes its operation the erase status, program status, v pp status and block lock status bits should be tested for errors. erase suspend status bit (sr6). the erase suspend status bit indicates that an erase opera- tion has been suspended or is going to be sus- pended in the addressed block. when the erase suspend status bit is high (set to 1), a program/ erase suspend command has been issued and the memory is waiting for a program/erase re- sume command. the erase suspend status should only be consid- ered valid when the program/erase controller sta- tus bit is high (program/erase controller inactive). sr7 is set within 30s of the program/erase sus- pend command being issued therefore the memo- ry may still complete the operation rather than entering the suspend mode. when a program/erase resume command is is- sued the erase suspend status bit returns low. erase status bit (sr5). the erase status bit can be used to identify if the memory has failed to verify that the block or bank has erased correctly. when the erase status bit is high (set to 1), the program/erase controller has applied the maxi- mum number of pulses to the block or bank and still failed to verify that it has erased correctly. the erase status bit should be read once the program/ erase controller status bit is high (program/erase controller inactive). once set high, the erase status bit can only be re- set low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program status bit (sr4). the program status bit is used to identify a program failure. when the program status bit is high (set to 1), the pro- gram/erase controller has applied the maximum number of pulses to the byte and still failed to ver- ify that it has programmed correctly. the program status bit should be read once the program/erase controller status bit is high (program/erase con- troller inactive). once set high, the program status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new command is issued, otherwise the new command will appear to fail. v pp status bit (sr3). the v pp status bit can be used to identify an invalid voltage on the v pp pin during program and erase operations. the v pp pin is only sampled at the beginning of a program or erase operation. indeterminate results can oc- cur if v pp becomes invalid during an operation. when the v pp status bit is low (set to 0), the volt- age on the v pp pin was sampled at a valid voltage; when the v pp status bit is high (set to 1), the v pp pin has a voltage that is below the v pp lockout voltage, v pplk , the memory is protected and pro- gram and erase operations cannot be performed.
21/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q once set high, the v pp status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program suspend status bit (sr2). the pro- gram suspend status bit indicates that a program operation has been suspended in the addressed block. when the program suspend status bit is high (set to 1), a program/erase suspend com- mand has been issued and the memory is waiting for a program/erase resume command. the pro- gram suspend status should only be considered valid when the program/erase controller status bit is high (program/erase controller inactive). sr2 is set within 5s of the program/erase sus- pend command being issued therefore the memo- ry may still complete the operation rather than entering the suspend mode. when a program/erase resume command is is- sued the program suspend status bit returns low. block protection status bit (sr1). the block protection status bit can be used to identify if a program or block erase operation has tried to modify the contents of a locked block. when the block protection status bit is high (set to 1), a program or erase operation has been at- tempted on a locked block. once set high, the block protection status bit can only be reset low by a clear status register com- mand or a hardware reset. if set high it should be reset before a new command is issued, otherwise the new command will appear to fail. reserved bit (sr0). sr0 is reserved. its value must be masked. table 8. status register bits note: logic level '1' is high, '0' is low. bit name type logic level definition sr7 p/e.c. status status '1' ready '0' busy sr6 erase suspend status status '1' erase suspended '0' erase in progress or completed sr5 erase status error '1' erase error '0' erase success sr4 program status error '1' program error '0' program success sr3 v pp status error '1' v pp invalid, abort '0' v pp ok sr2 program suspend status status '1' program suspended '0' program in progress or completed sr1 block protection status error '1' program/erase on protected block, abort '0' no operation to protected blocks sr0 reserved
m58cr064c, m58cr064d, m58cr064p, m58cr064q 22/70 configuration register the configuration register is used to configure the type of bus access that the memory will per- form. refer to read modes section for details on read operations. the configuration register is set through the command interface. after a reset or power-up the device is configured for asynchronous page read (cr15 = 1). the configuration register bits are described in table 9. they specify the selec- tion of the burst length, burst type, burst x latency and the read operation. refer to figures 6 and 7 for examples of synchronous burst configurations. read select bit (cr15) the read select bit, cr15, is used to switch be- tween asynchronous and synchronous bus read operations. when the read select bit is set to 1, read operations are asynchronous; when the read select bit is set to 0, read operations are synchronous. synchronous burst read is support- ed in both parameter and main blocks and can be performed across banks. on reset or power-up the read select bit is set to1 for asynchronous access. x-latency bits (cr13-cr11) the x-latency bits are used during synchronous read operations to set the number of clock cycles between the address being latched and the first data becoming available. for correct operation the x-latency bits can only assume the values in ta- ble 9, configuration register. the correspondence between x-latency settings and the maximum sustainable frequency must be calculated taking into account some system pa- rameters. two conditions must be satisfied: 1. depending on whether t avk_cpu or t delay is supplied either one of the following two equations must be satisfied: (n + 1) t k 3 t acc - t avk_cpu + t qvk_cpu (n + 2) t k 3 t acc + t delay + t qvk_cpu 2. and also t k > t kqv + t qvk_cpu where n is the chosen x-latency configuration code t k is the clock period t avk_cpu is clock to address valid, l low, or e low, whichever occurs last t delay is address valid, l low, or e low to clock, whichever occurs last t qvk_cpu is the data setup time required by the system cpu, t kqv is the clock to data valid time t acc is the random access time of the device. refer to figure 6, x-latency and data output configuration example. power-down bit (cr10) the power-down bit is used to enable or disable the power-down function. when the power-down bit is set to 0 the power- down function is disabled. if the reset/power- down, rp , pin goes low, v il , the device is reset and the supply current, i dd, is reduced to the standby value, i dd3 . when the power-down bit is set to 1 the power- down function is enabled. if the reset/power- down, rp , pin goes low, v il , the device goes into the power-down state and the supply current, i dd, is reduced to the power-down value, i dd2 . the recovery time after a reset/power-down, rp , pulse is significantly longer when power-down is enabled (see table 24). after a reset the power-down bit is set to 0. wait configuration bit (cr8) in burst mode the wait bit controls the timing of the wait output pin, wait . when the wait bit is 0 the wait output pin is asserted during the wait state. when the wait bit is 1 (default) the wait output pin is asserted one clock cycle before the wait state. wait is asserted during a continuous burst and also during a 4 or 8 burst length if no-wrap config- uration is selected. wait is not asserted during asynchronous reads, single synchronous reads or during latency in synchronous reads. burst type bit (cr7) the burst type bit is used to configure the se- quence of addresses read as sequential or inter- leaved. when the burst type bit is 0 the memory outputs from interleaved addresses; when the burst type bit is 1 (default) the memory outputs from sequential addresses. see tables 10, burst type definition, for the sequence of addresses output from a given starting address in each mode. valid clock edge bit (cr6) the valid clock edge bit, cr6, is used to config- ure the active edge of the clock, k, during syn- chronous burst read operations. when the valid clock edge bit is 0 the falling edge of the clock is the active edge; when the valid clock edge bit is 1 the rising edge of the clock is active. wrap burst bit (cr3) the burst reads can be confined inside the 4 or 8 word boundary (wrap) or overcome the boundary (no wrap). the wrap burst bit is used to select be- tween wrap and no wrap. when the wrap burst bit is set to 0 the burst read wraps; when it is set to 1 the burst read does not wrap.
23/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q burst length bits (cr2-cr0) the burst length bits set the number of words to be output during a synchronous burst read oper- ation as result of a single address latch cycle. they can be set for 4 words, 8 words or continu- ous burst, where all the words are read sequential- ly. in continuous burst mode the burst sequence can cross bank boundaries. in continuous burst mode or in 4, 8 words no-wrap, depending on the starting address, the device as- serts the wait output to indicate that a delay is necessary before the data is output. if the starting address is aligned to a 4 word boundary no wait states are needed and the wait output is not asserted. if the starting address is shifted by 1,2 or 3 posi- tions from the four word boundary, wait will be asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 64 word boundary, to indicate that the device needs an internal delay to read the successive words in the array. wait will be asserted only once during a continuous burst access. see also table 10, burst type definition. cr14, cr9, cr5 and cr4 are reserved for future use. table 9. configuration register bit description value description cr15 read select 0 synchronous read 1 asynchronous read (default at power-on) cr14 reserved cr13-cr11 x-latency 010 2 clock latency 011 3 clock latency 100 4 clock latency 101 5 clock latency 111 reserved other configurations reserved cr10 power-down 0 power-down disabled 1 power-down enabled cr9 reserved cr8 wait configuration 0 wait is active during wait state 1 wait is active one data cycle before wait state (default) cr7 burst type 0 interleaved 1 sequential (default) cr6 valid clock edge 0 falling clock edge 1 rising clock edge cr5-cr4 reserved cr3 wrap burst 0 wrap 1 no wrap cr2-cr0 burst length 001 4 words 010 8 words 111 continuous (cr7 m ust be set to 1)
m58cr064c, m58cr064d, m58cr064p, m58cr064q 24/70 table 10. burst type definition mode start address 4 words 8 words continuous burst sequential interleaved sequential interleaved wrap 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6... 1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7... 2 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8... 3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9... ... 7 7-4-5-6 7-6-5-4 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13... ... 60 60-61-62-63-64-65-66... 61 61-62-63-wait-64-65-66... 62 62-63-wait-wait-64-65-66... 63 63-wait-wait-wait-64-65- 66... sequential interleaved sequential interleaved no-wrap 0 0-1-2-3 0-1-2-3-4-5-6-7 same as for wrap (wrap /no wrap has no effect on continuous burst ) 1 1-2-3-4 1-2-3-4-5-6-7-8 2 2-3-4-5 2-3-4-5-6-7-8-9... 3 3-4-5-6 3-4-5-6-7-8-9-10 ... 7 7-8-9-10 7-8-9-10-11-12-13-14 ... 60 60-61-62-63 60-61-62-63-64-65-66- 67 61 61-62-63-wait-64 61-62-63-wait-64-65- 66-67-68 62 62-63-wait-wait- 64-65 62-63-wait-wait-64- 65-66-67-68-69 63 63-wait-wait- wait-64-65-66 63-wait-wait-wait- 64-65-66-67-68-69-70
25/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q figure 6. x-latency and data output configuration example figure 7. wait configuration example ai90005 a21-a0 valid address k l dq15-dq0 valid data x-latency valid data tacc tavk_cpu tk tqvk_cpu tqvk_cpu tkqv 1st cycle 2nd cycle 3rd cycle 4th cycle note. settings shown: x-latency = 4, data output held for one clock cycle e tdelay ai90006b a21-a0 valid address k l dq15-dq0 valid data wait cr8 = '0' wait cr8 = '1' valid data not valid valid data e
m58cr064c, m58cr064d, m58cr064p, m58cr064q 26/70 read modes read operations can be performed in two different ways depending on the settings in the configura- tion register. if the clock signal is dont care for the data output, the read operation is asynchro- nous; if the data output is synchronized with clock, the read operation is synchronous. the read mode and data output format are deter- mined by the configuration register. (see config- uration register section for details). all banks supports both asynchronous and synchronous read operations. the dual bank architecture al- lows read operations in one bank, while write op- erations are being executed in the other (see tables 11 and 12). asynchronous read mode in asynchronous read operations the clock signal is dont care. the device outputs the data corre- sponding to the address latched, that is the mem- ory array, status register, common flash interface or electronic signature depending on the command issued. cr15 in the configuration reg- ister must be set to 1 for asynchronous opera- tions. in asynchronous read mode a page of data is in- ternally read and stored in a page buffer. the page has a size of 4 words and is addressed by a0 and a1 address inputs. the address inputs a0 and a1 are not gated by latch enable in asyn- chronous read mode. the first read operation within the page has a longer access time (t acc , random access time), subsequent reads within the same page have much shorter access times. if the page changes then the normal, longer timings apply again. asynchronous read operations can be performed in two different ways, asynchronous random ac- cess read and asynchronous page read. only asynchronous page read takes full advantage of the internal page storage so different timings are applied. see table 20, asynchronous read ac character- istics, figure 10, asynchronous random access read ac waveform and figure 11, asynchronous page read ac waveform for details. synchronous burst read mode in synchronous burst read mode the data is out- put in bursts synchronized with the clock. it is pos- sible to perform burst reads across bank boundaries. synchronous burst read mode can only be used to read the memory array. for other read opera- tions, such as read status register, read cfi and read electronic signature, single synchro- nous read or asynchronous random access read must be used. in synchronous burst read mode the flow of the data output depends on parameters that are con- figured in the configuration register. a burst sequence is started at the first clock edge (rising or falling depending on valid clock edge bit cr6 in the configuration register) after the falling edge of latch enable or chip enable, whichever occurs last. addresses are internally incremented and after a delay of 2 to 5 clock cycles (x latency bits cr13-cr11) the corresponding data are out- put on each clock cycle. the number of words to be output during a syn- chronous burst read operation can be configured as 4 or 8 words or continuous (burst length bits cr2-cr0). the data can be configured to remain valid for one or two clock cycles (data output con- figuration bit cr9). the order of the data output can be modified through the burst type and the wrap burst bits in the configuration register. the burst sequence may be configured to be sequential or interleaved (cr7). the burst reads can be confined inside the 4 or 8 word boundary (wrap) or overcome the boundary (no wrap). if the starting address is aligned to the burst length (4 or 8 words), the wrapped configuration has no impact on the output sequence. interleaved mode is not allowed in con- tinuous burst read mode or with no wrap se- quences. a wait signal may be asserted to indicate to the system that an output delay will occur. this delay will depend on the starting address of the burst se- quence; the worst case delay will occur when the sequence is crossing a 64 word boundary and the starting address was at the end of a four word boundary. wait is asserted during the wait state and at the end of 4- and 8-word burst. it is deasserted during the x latency and when output data are valid. in continuous burst read mode a wait state will oc- cur when crossing the first 64 word boundary. if the burst starting address is aligned to a 4 word page, the wait state will not occur. the wait signal is active low. the wait signal is meaningful only in synchronous burst read mode, in other modes, wait is not asserted (ex- cept for read array mode). see table 21, synchronous read ac character- istics and figure 12, synchronous burst read ac waveform for details. single synchronous read mode single synchronous read operations are similar to synchronous burst read operations except that only the first data output after the x latency is valid. other configuration register parameters have no effect on single synchronous read operations.
27/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q synchronous single reads are used to read the electronic signature, status register, cfi, block protection status, configuration register status or protection register. when the addressed bank is in read cfi, read status register or read electronic signature mode, the wait signal is al- ways deasserted. see table 21, synchronous read ac character- istics and figure 13, single synchronous read ac waveform for details. dual operations and multiple bank architecture the dual operations feature simplifies the soft- ware management of the device and allows code to be executed from one bank while the other bank is being programmed or erased. the dual operations feature means that while pro- gramming or erasing in one bank, read opera- tions are possible in the other bank with zero latency (only one bank at a time is allowed to be in program or erase mode). if a read operation is re- quired in a bank which is programming or erasing, the program or erase operation can be suspend- ed. also if the suspended operation was erase then a program command can be issued to anoth- er block, so the device can have one block in erase suspend mode, one programming and the other bank in read mode. bus read operations are allowed in the other bank between setup and confirm cycles of program or erase operations. the combination of these features means that read operations are possible at any moment. tables 11 and 12 show the dual operations possi- ble in the other bank and in the same bank. for a complete list of possible commands refer to ap- pendix d, command interface state tables. table 11. dual operations allowed in other bank table 12. dual operations allowed in same bank note: 1. not allowed in the block or word that is being erased or programmed. status of bank commands allowed in other bank read array read status register read cfi query read electronic signature program block erase program/ erase suspend program/ erase resume idle yes yes yes yes yes yes yes yes programming yes yes yes yes CCCC erasing yes yes yes yes C C C C program suspended yes yes yes yes C C C yes erase suspended yes yes yes yes yes C C yes status of bank commands allowed in same bank read array read status register read cfi query read electronic signature program block erase program/ erase suspend program/ erase resume idle yes yes yes yes yes yes yes yes programming C yesCCCCyesC erasing C yesCCCCyesC program suspended ye s (1) ye s ye s ye s C C C ye s erase suspended ye s (1) yes yes yes ye s (1) CCyes
m58cr064c, m58cr064d, m58cr064p, m58cr064q 28/70 block locking the m58cr064 features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. this locking scheme has three levels of protection. n lock/unlock - this first level allows software- only control of block locking. n lock-down - this second level requires hardware interaction before locking can be changed. n v pp v pplk - the third level offers a complete hardware protection against program and erase on all blocks (m58cr064c/d only). the first two levels (lock/unlock and lock-down) are available in m58cr064c/d and m58cr064p/ q. the third level (v pp v pplk ) is only available for the m58cr064c/d versions, in the m58cr064p/q this feature has been disabled. for all devices the protection status of each block can be set to locked, unlocked, and lock-down. table 13, defines all of the possible protection states (wp , dq1, dq0), and appendix c, figure 26, shows a flowchart for the locking operations. reading a blocks lock status the lock status of every block can be read in the read electronic signature mode of the device. to enter this mode write 90h to the device. subse- quent reads at the address specified in table 6, will output the protection status of that block. the lock status is represented by dq0 and dq1. dq0 indicates the block lock/unlock status and is set by the lock command and cleared by the unlock command. it is also automatically set when enter- ing lock-down. dq1 indicates the lock-down sta- tus and is set by the lock-down command. it cannot be cleared by software, only by a hardware reset or power-down. the following sections explain the operation of the locking system. locked state the default status of all blocks on power-up or af- ter a hardware reset is locked (states (0,0,1) or (1,0,1)). locked blocks are fully protected from any program or erase. any program or erase oper- ations attempted on a locked block will return an error in the status register. the status of a locked block can be changed to unlocked or lock-down using the appropriate software com- mands. an unlocked block can be locked by issu- ing the lock command. unlocked state unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. all unlocked blocks return to the locked state after a hardware reset or when the device is powered-down. the status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. a locked block can be un- locked by issuing the unlock command. lock-down state blocks that are locked-down (state (0,1,x))are protected from program and erase operations (as for locked blocks) but their protection status can- not be changed using software commands alone. a locked or unlocked block can be locked-down by issuing the lock-down command. locked- down blocks revert to the locked state when the device is reset or powered-down. the lock-down function is dependent on the wp input pin. when wp =0 (v il ), the blocks in the lock-down state (0,1,x) are protected from pro- gram, erase and protection status changes. when wp =1 (v ih ) the lock-down function is disabled (1,1,x) and locked-down blocks can be individual- ly unlocked to the (1,1,0) state by issuing the soft- ware command, where they can be erased and programmed. these blocks can then be re-locked (1,1,1) and unlocked (1,1,0) as desired while wp remains high. when wp is low , blocks that were previously locked-down return to the lock-down state (0,1,x) regardless of any changes made while wp was high. device reset or power-down resets all blocks , including those in lock-down, to the locked state. locking operations during erase suspend changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. this is useful in the case when another block needs to be updated while an erase operation is in progress. to change block locking during an erase opera- tion, first write the erase suspend command, then check the status register until it indicates that the erase operation has been suspended. next write the desired lock command sequence to a block and the lock status will be changed. after complet- ing any desired lock, read, or program operations, resume the erase operation with the erase re- sume command. if a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. locking operations cannot be performed during a program suspend. refer to appendix d, com- mand interface state table, for detailed informa- tion on which commands are valid during erase suspend.
29/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q table 13. lock status note: 1. the lock status is defined by the write protect pin and by dq1 (1 for a locked-down block) and dq0 (1 for a locked block) a s read in the read electronic signature command with a1 = v ih and a0 = v il . 2. all blocks are locked at power-up, so the default configuration is 001 or 101 according to wp status. 3. a wp transition to v ih on a locked block will restore the previous dq0 value, giving a 111 or 110. current protection status (1) (wp , dq1, dq0) next protection status (1) (wp , dq1, dq0) current state program/erase allowed after block lock command after block unlock command after block lock-down command after wp transition 1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0 1,0,1 (2) no 1,0,1 1,0,0 1,1,1 0,0,1 1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0 0,0,1 (2) no 0,0,1 0,0,0 0,1,1 1,0,1 0,1,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,0 (3)
m58cr064c, m58cr064d, m58cr064p, m58cr064q 30/70 program and erase times and endurance cycles the program and erase times and the number of program/ erase cycles per block are shown in ta- ble 14. in the m58cr064 the maximum number of program/ erase cycles depends on the voltage supply used. table 14. program, erase times and program, erase endurance cycles note: 1. t a = C40 to 85c; v dd = 1.65v to 2v; v ddq = 1.65v to 3.3v. 2. the difference between preprogrammed and not preprogrammed is not significant (?30ms). 3. excludes the time needed to execute the command sequence. parameter condition min typ typical after 100k w/e cycles max unit v pp = v dd parameter block (4 kword) erase (2) 0.3 1 2.5 s main block (32 kword) erase preprogrammed 0.8 3 4 s not preprogrammed 1.1 4 s bank a (16mbit) erase preprogrammed 11 s not preprogrammed 18 s bank b (48mbit) erase preprogrammed 33 s not preprogrammed 54 s parameter block (4 kword) program (3) 40 ms main block (32 kword) program (3) 300 ms word program (3) 10 10 100 s program suspend latency 5 10 s erase suspend latency 5 20 s program/erase cycles (per block) main blocks 100,000 cycles parameter blocks 100,000 cycles v pp = v pph parameter block (4 kword) erase 0.3 2.5 s main block (32 kword) erase 0.9 4 s bank a (16mbit) erase 13 s bank b (48mbit) erase 39 s 4mbit program quadruple word 510 ms word/ double word/ quadruple word program (3) 8 100 s parameter block (4 kword) program (3) quadruple word 8 ms word 32 ms main block (32 kword) program (3) quadruple word 64 ms word 256 ms program/erase cycles (per block) main blocks 1000 cycles parameter blocks 2500 cycles
31/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 15. absolute maximum ratings value symbol parameter min max unit t a ambient operating temperature C40 85 c t bias temperature under bias C40 125 c t stg storage temperature C55 155 c v io input or output voltage C0.5 v ddq +0.5 v v dd supply voltage C0.5 2.7 v v ddq input/output supply voltage C0.5 3.6 v v pp program voltage C0.5 13 v i o output short circuit current 100 ma t vpph time for v pp at v pph 100 hours
m58cr064c, m58cr064d, m58cr064p, m58cr064q 32/70 dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 16, operating and ac measurement conditions. designers should check that the operating conditions in their circuit match the operating conditions when rely- ing on the quoted parameters. table 16. operating and ac measurement conditions figure 8. ac measurement i/o waveform figure 9. ac measurement load circuit table 17. capacitance note: sampled only, not 100% tested. m58cr064c, m58cr064d, m58cr064p, m58cr064q parameter 85 90 100 120 unit min max min max min max min max v dd supply voltage 1.8 2.0 1.7 2.0 1.65 2.0 1.65 2.0 v v ddq supply voltage 1.8 3.3 1.7 3.3 1.65 3.3 1.65 3.3 v v pp supply voltage (factory environment) 11.4 12.6 11.4 12.6 11.4 12.6 11.4 12.6 v v pp supply voltage (application environment) C0.4 v ddq +0.4 C0.4 v ddq +0.4 C0.4 v ddq +0.4 C0.4 v ddq +0.4 v ambient operating temperature C40 85 C40 85 C40 85 C40 85 c load capacitance (c l ) 30 30 30 30 pf input rise and fall times 4 4 4 4 ns input pulse voltages 0 to v ddq 0 to v ddq 0 to v ddq 0 to v ddq v input and output timing ref. voltages v ddq /2 v ddq /2 v ddq /2 v ddq /2 v ai06161 v ddq 0v v ddq /2 ai06162 v ddq c l c l includes jig capacitance 16.7k w device under test 0.1f v dd 0.1f v ddq 16.7k w symbol parameter test condition min max unit c in input capacitance v in = 0v 68pf c out output capacitance v out = 0v 812pf
33/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q table 18. dc characteristics - currents note: 1. sampled only, not 100% tested. 2. v dd dual operation current is the sum of read and program or erase currents. symbol parameter test condition min typ max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 1 a i dd1 supply current asynchronous read (f=6mhz) e = v il , g = v ih 36ma supply current synchronous read (f=40mhz) 4 word 6 13 ma 8 word 8 14 ma continuous 6 10 ma supply current synchronous read (f=54mhz) 4 word 7 16 ma 8 word 10 18 ma continuous 13 25 ma i dd2 supply current (power-down) rp = v ss 0.2v 210a i dd3 supply current (standby) e = v dd 0.2v 10 50 a i dd4 (1) supply current (program) v pp = v pph 815ma v pp = v dd 10 20 ma supply current (erase) v pp = v pph 815ma v pp = v dd 10 20 ma i dd5 (1,2) supply current (dual operations) program/erase in one bank, asynchronous read in another bank 13 26 ma program/erase in one bank, synchronous read in another bank 16 30 ma i dd6 (1) supply current program/ erase suspended (standby) e = v dd 0.2v 10 50 a i pp1 (1) v pp supply current (program) v pp = v pph 25ma v pp = v dd 0.2 5 a v pp supply current (erase) v pp = v pph 25ma v pp = v dd 0.2 5 a i pp2 v pp supply current (read) v pp = v pph 100 400 a v pp v dd 0.2 5 a i pp3 (1) v pp supply current (standby) v pp v dd 0.2 5 a
m58cr064c, m58cr064d, m58cr064p, m58cr064q 34/70 table 19. dc characteristics - voltages symbol parameter test condition min typ max unit v il input low voltage C0.5 0.4 v v ih input high voltage v ddq C0.4 v ddq + 0.4 v v ol output low voltage i ol = 100a 0.1 v v oh output high voltage i oh = C100a v ddq C0.1 v v pp1 v pp program voltage-logic program, erase 1 1.8 1.95 v v pph v pp program voltage factory program, erase 11.4 12 12.6 v v pplk program or erase lockout 0.9 v v lko v dd lock voltage 1v v rph rp pin extended high voltage 3.3 v
35/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q figure 10. asynchronous random access read ac waveforms ai90009b tavav tavqv telqx tehqx tglqv tglqx tghqx dq0-dq15 e g telqv tehqz tghqz valid a0-a21 valid valid l tellh tllqv tlllh tavlh tlhax taxqx wait teltv tehtz note. write enable, w, is high. valid address latch outputs enabled data valid standby tlhgl hi-z hi-z tgltv
m58cr064c, m58cr064d, m58cr064p, m58cr064q 36/70 figure 11. asynchronous page read ac waveforms ai90048c a2-a21 e g a0-a1 valid address l dq0-dq15 valid address valid address valid address valid address valid data valid data valid data valid data tlhax tavlh tllqv tavqv1 tglqx tlllh tellh wait tavav telqv telqx teltv tglqv valid address latch outputs enabled valid data standby tlhgl hi-z tgltv
37/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q table 20. asynchronous read ac characteristics note: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv - t glqv after the falling edge of e without increasing t elqv . symbol alt parameter m58cr064 unit 85 90 100 120 read timings t avav t rc address valid to next address valid min 85 90 100 120 ns t avqv t acc address valid to output valid (random) max 85 90 100 120 ns t avqv1 t pa g e address valid to output valid (page) max 30 30 45 45 ns t axqx (1) t oh address transition to output transition min 0000ns t eltv chip enable low to wait valid max 14 14 14 18 ns t elqv (2) t ce chip enable low to output valid max 85 90 100 120 ns t elqx (1) t lz chip enable low to output transition min 0000ns t ehtz chip enable high to wait hi-z max 20 20 20 20 ns t ehqx (1) t oh chip enable high to output transition min 0000ns t ehqz (1) t hz chip enable high to output hi-z max 20 20 20 20 ns t glqv (2) t oe output enable low to output valid max 25 25 25 25 ns t glqx (1) t olz output enable low to output transition min 0000ns t gltv output enable low to wait valid max 14 14 14 18 ns t ghqx (1) t oh output enable high to output transition min 0000ns t ghqz (1) t df output enable high to output hi-z max 20 20 20 20 ns latch timings t av lh t avadvh address valid to latch enable high min 10 10 10 10 ns t ellh t eladvh chip enable low to latch enable high min 10 10 10 10 ns t lhax t advhax latch enable high to address transition min 10 10 10 10 ns t lllh t advladvh latch enable pulse width min 10 10 10 10 ns t llqv t advlqv latch enable low to output valid (random) max 85 90 100 120 ns t lhgl t advhgl latch enable high to output enable low min 10 10 10 10 ns
m58cr064c, m58cr064d, m58cr064p, m58cr064q 38/70 figure 12. synchronous burst read ac waveforms ai90010b dq0-dq15 e g a0-a21 l wait k valid valid valid address tlllh tavlh tglqx tavkh tllkh telkh tkhax tkhqx tkhqv not valid valid note 1 note 2 note 2 tkhtx tkhtv tehqx tehqz tghqx tghqz tkhkh tkhtx tkhkl tklkh hi-z valid teltv tehtz address latch x latency valid data flow boundary crossing valid data standby note 1. the number of clock cycles to be inserted depends on the x latency set in the configuration register. 2. the wait signal can be configured to be active during wait state or one cycle before. 3. address latched and data output on the rising clock edge. tehel tkhqv tkhqx tkhqv tkhqx hi-z tgltv
39/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q figure 13. single synchronous read ac waveforms ai06232 dq0-dq15 e g a0-a21 l wait (2) k (4) valid not valid valid address tlllh tavlh tglqv tavkh tllkh telkh tkhax not valid not valid note 1 tehqx tehqz tghqx tghqz tkhkh tkhkl tklkh hi-z not valid teltv tkhqv tehtz note 1. the number of clock cycles to be inserted depends on the x latency set in the configuration register. 2. the wait signal is configured to be active during wait state. 3. wait is always deasserted when addressed bank is in read cfi, read sr or read electronic signature mode. wait signals valid data if the addressed bank is in read array mode. 4. address latched and data output on the rising clock edge. not valid tglqx tehel hi-z tgltv note 3
m58cr064c, m58cr064d, m58cr064p, m58cr064q 40/70 table 21. synchronous read ac characteristics note: 1. sampled only, not 100% tested. 2. for other timings please refer to table 20, asynchronous read ac characteristics. symbol alt parameter m58cr064 unit 85 90 100 120 synchronous read timings t avkh t av clkh address valid to clock high min 7777ns t elkh t elclkh chip enable low to clock high min 7777ns t eltv chip enable low to wait valid max 14 14 14 18 ns t ehel chip enable pulse width (subsequent synchronous reads) min20202020ns t ehtz chip enable high to wait hi-z max 20 20 20 20 ns t khax t clkhax clock high to address transition min 10 10 10 10 ns t khqv t khtv t clkhqv clock high to output valid clock high to wait valid max14141418ns t khqx t khtx t clkhqx clock high to output transition clock high to wait transition min4444ns t llkh t advlclkh latch enable low to clock high min 7777ns clock specifications t khkh t clk clock period (f=40mhz) min 25 ns clock period (f=54mhz) min 18 18 18 ns t khkl t clkhclkl clock high to clock low min 5555ns t klkh t clklclkh clock low to clock high max 5555ns
41/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q figure 14. write ac waveforms, write enable controlled e g w dq0-dq15 command cmd or data status register v pp valid address a0-a21 tavav tqvvpl tavwh twhax program or erase telwl twheh twhdx tdvwh twlwh twhwl tvphwh set-up command confirm command or data input status register read 1st polling telqv ai90011b twphwh wp twhgl tqvwpl twhel bank address valid address l tavlh tlllh tellh tlhax tghwl twhqv twhwpl twhvpl twhkv k twhll twhav
m58cr064c, m58cr064d, m58cr064p, m58cr064q 42/70 table 22. write ac characteristics, write enable controlled note: 1. sampled only, not 100% tested. 2. t whel has the values shown when reading in the targeted bank. system designers should take this into account and may insert a software no-op instruction to delay the first read in the same bank after issuing a command. if the read operation is in a diff erent bank t whel is 0ns. symbol alt parameter m58cr064 unit 85 90 100 120 write enable controlled timings t avav t wc address valid to next address valid min 85 90 100 120 ns t avlh address valid to latch enable high min 10 10 10 10 ns t avw h t wc address valid to write enable high min 60 60 60 60 ns t dvwh t ds input valid to write enable high min 40 40 40 40 ns t ellh chip enable low to latch enable high min 10 10 10 10 ns t elwl t cs chip enable low to write enable low min 0 0 0 0 ns t elqv chip enable low to output valid min 85 90 100 120 ns t ghwl output enable high to write enable low min 20 20 20 20 ns t lhax latch enable high to address transition min 10 10 10 10 ns t lllh latch enable pulse width min 10 10 10 10 ns t whav write enable high to address valid min 0 0 0 0 ns t whax t ah write enable high to address transition min 0 0 0 0 ns t whdx t dh write enable high to input transition min 0 0 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 0 0 ns t whel (2) write enable high to chip enable low min 50 50 50 50 ns t whgl write enable high to output enable low min 0 0 0 0 ns t whll write enable high to latch enable low min 0 0 0 0 ns t whkv write enable high to clock valid min 25 25 25 25 ns t whwl t wph write enable high to write enable low min 30 30 30 30 ns t whqv write enable high to output valid min 105 110 120 140 ns t wlwh t wp write enable low to write enable high min 50 50 50 50 ns protection timings t qvvpl output (status register) valid to v pp low min 0 0 0 0 ns t qvwpl output (status register) valid to write protect low min 0 0 0 0 ns t vphwh t vps v pp high to write enable high min 200 200 200 200 ns t whvpl write enable high to v pp low min 200 200 200 200 ns t whwpl write enable high to write protect low min 200 200 200 200 ns t wphwh write protect high to write enable high min 200 200 200 200 ns
43/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q figure 15. write ac waveforms, chip enable controlled w g e dq0-dq15 command cmd or data status register v pp valid address a0-a21 tavav tqvvpl taveh tehax program or erase twlel tehwh tehdx tdveh teleh tehel tvpheh set-up command confirm command or data input status register read 1st polling telqv ai90012b twpheh wp tehgl tqvwpl twhel bank address valid address l tavlh tlllh tlhax tghel tehwpl tehvpl twhkv k tellh
m58cr064c, m58cr064d, m58cr064p, m58cr064q 44/70 table 23. write ac characteristics, chip enable controlled note: 1. sampled only, not 100% tested. 2. t whel has the values shown when reading in the targeted bank. system designers should take this into account and may insert a software no-op instruction to delay the first read in the same bank after issuing a command. if the read operation is in a diff erent bank t whel is 0ns. symbol alt parameter m58cr064 unit 85 90 100 120 chip enable controlled timings t avav t wc address valid to next address valid min 85 90 100 120 ns t av eh t wc address valid to chip enable high min 60 60 60 60 ns t avlh address valid to latch enable high min 10 10 10 10 ns t dveh t ds input valid to write enable high min 40 40 40 40 ns t ehax t ah chip enable high to address transition min 0 0 0 0 ns t ehdx t dh chip enable high to input transition min 0 0 0 0 ns t ehel t wph chip enable high to chip enable low min 30 30 30 30 ns t ehgl chip enable high to output enable low min 0 0 0 0 ns t ehwh t ch chip enable high to write enable high min 0 0 0 0 ns t eleh t wp chip enable low to chip enable high min 60 60 60 60 ns t ellh chip enable low to latch enable high min 10 10 10 10 ns t elqv latch enable low to output valid min 85 90 100 120 ns t ghel output enable high to chip enable low min 20 20 20 20 ns t lhax latch enable high to address transition min 10 10 10 10 ns t lllh latch enable pulse width min 10 10 10 10 ns t whel (2) write enable high to chip enable low min 50 50 50 50 ns t whkv write enable high to clock valid min 25 25 25 25 ns t wlel t cs write enable low to chip enable low min 0 0 0 0 ns protection timings t ehvpl chip enable high to v pp low min 200 200 200 200 ns t ehwpl chip enable high to write protect low min 200 200 200 200 ns t qvvpl output (status register) valid to v pp low min 0 0 0 0 ns t qvwpl output (status register) valid to write protect low min 0 0 0 0 ns t vpheh t vps v pp high to chip enable high min 200 200 200 200 ns t wpheh write protect high to chip enable high min 200 200 200 200 ns
45/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q figure 16. reset and power-up ac waveforms table 24. reset and power-up ac characteristics note: 1. the device reset is possible but not guaranteed if t plph < 50ns. 2. sampled only, not 100% tested. 3. it is important to assert rp in order to allow proper cpu initialization during power-up or reset. symbol parameter test condition 85 90 100 120 unit t plwl t plel t plgl t plll reset low to write enable low, chip enable low, output enable low, latch enable low during program min 10 10 10 10 s during erase min 20 20 20 20 s other conditions min 80 80 80 80 ns t plph (1,2) rp pulse width min 50 50 50 50 ns t vdhph (3) supply voltages high to reset high min50505050s ai90013c w, rp e, g, vdd, vddq tvdhph tplph power-up reset tplwl tplel tplgl tplll l
m58cr064c, m58cr064d, m58cr064p, m58cr064q 46/70 package mechanical figure 17. tfbga56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, bottom view package outline note: drawing is not to scale. table 25. tfbga56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.010 1.200 0.0398 0.0472 a1 0.250 0.400 0.0098 0.0157 a2 0.790 0.0311 b 0.400 0.350 0.450 0.0157 0.0138 0.0177 d 6.500 6.400 6.600 0.2559 0.2520 0.2598 d1 5.250 C C 0.2067 C C ddd 0.100 0.0039 e 10.000 9.900 10.100 0.3937 0.3898 0.3976 e1 4.500 C C 0.1772 C C e 0.750 C C 0.0295 C C fd 0.625 C C 0.0246 C C fe 2.750 C C 0.1083 C C sd 0.375 C C 0.0148 C C e1 e d1 d a2 a1 a bga-z20 ddd e e sd b fe fd ball "a1"
47/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q figure 18. tfbga56 daisy chain - package connections (top view through package) d c b a 8 7 6 5 4 3 2 1 g f e ai07731
m58cr064c, m58cr064d, m58cr064p, m58cr064q 48/70 figure 19. tfbga56 daisy chain - pcb connection proposal (top view through package) d c b a 8 7 6 5 4 3 2 1 g f e ai07755 end point start point
49/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q part numbering table 26. ordering information scheme table 27. daisy chain ordering scheme d evices are shipped from the factory with the memory content bits erased to 1. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m58cr064c 85 zb 6 t device type m58 architecture c = dual bank, burst mode operating voltage r = v dd = 1.65v to 2.0v, v ddq = 1.65v to 3.3v device function 064c = 64 mbit (x16), dual bank: 1/4-3/4 partitioning, top boot 064d = 64 mbit (x16), dual bank: 1/4-3/4 partitioning, bottom boot 064p = 64 mbit (x16), dual bank: 1/4-3/4 partitioning, top boot, v pp protection feature disabled 064q = 64 mbit (x16), dual bank: 1/4-3/4 partitioning, bottom boot, v pp protection feature disabled speed 85 = 85ns 90 = 90ns 10 = 100ns 12 = 120ns package zb = tfbga56: 6.5 x 10mm, 0.75 mm pitch temperature range 6 = C40 to 85c option t = tape & reel packing example: m58cr064 -zb t device type m58cr064 daisy chain zb = tfbga56: 6.5 x 10mm , 0.75 mm pitch option t = tape & reel packing
m58cr064c, m58cr064d, m58cr064p, m58cr064q 50/70 appendix a. block address tables table 28. top boot block addresses, m58cr064c, m58cr064p bank # size (kword) address range bank a 0 4 3ff000-3fffff 1 4 3fe000-3fefff 2 4 3fd000-3fdfff 3 4 3fc000-3fcfff 4 4 3fb000-3fbfff 5 4 3fa000-3fafff 6 4 3f9000-3f9fff 7 4 3f8000-3f8fff 8 32 3f0000-3f7fff 9 32 3e8000-3effff 10 32 3e0000-3e7fff 11 32 3d8000-3dffff 12 32 3d0000-3d7fff 13 32 3c8000-3cffff 14 32 3c0000-3c7fff 15 32 3b8000-3bffff 16 32 3b0000-3b7fff 17 32 3a8000-3affff 18 32 3a0000-3a7fff 19 32 398000-39ffff 20 32 390000-397fff 21 32 388000-38ffff 22 32 380000-387fff 23 32 378000-37ffff 24 32 370000-377fff 25 32 368000-36ffff 26 32 360000-367fff 27 32 358000-35ffff 28 32 350000-357fff 29 32 348000-34ffff 30 32 340000-347fff 31 32 338000-33ffff 32 32 330000-337fff 33 32 328000-32ffff 34 32 320000-327fff 35 32 318000-31ffff 36 32 310000-317fff 37 32 308000-30ffff 38 32 300000-307fff bank b 39 32 2f8000-2fffff 40 32 2f0000-2f7fff 41 32 2e8000-2effff 42 32 2e0000-2e7fff 43 32 2d8000-2dffff 44 32 2d0000-2d7fff 45 32 2c8000-2cffff 46 32 2c0000-2c7fff 47 32 2b8000-2bffff 48 32 2b0000-2b7fff 49 32 2a8000-2affff 50 32 2a0000-2a7fff 51 32 298000-29ffff 52 32 290000-297fff 53 32 288000-28ffff 54 32 280000-287fff 55 32 278000-27ffff 56 32 270000-277fff 57 32 268000-26ffff 58 32 260000-267fff 59 32 258000-25ffff 60 32 250000-257fff 61 32 248000-24ffff 62 32 240000-247fff 63 32 238000-23ffff 64 32 230000-237fff 65 32 228000-22ffff 66 32 220000-227fff 67 32 218000-21ffff 68 32 210000-217fff 69 32 208000-20ffff 70 32 200000-207fff 71 32 1f8000-1fffff 72 32 1f0000-1f7fff 73 32 1e8000-1effff 74 32 1e0000-1e7fff 75 32 1d8000-1dffff 76 32 1d0000-1d7fff 77 32 1c8000-1cffff 78 32 1c0000-1c7fff
51/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q bank b 79 32 1b8000-1bffff 80 32 1b0000-1b7fff 81 32 1a8000-1affff 82 32 1a0000-1a7fff 83 32 198000-19ffff 84 32 190000-197fff 85 32 188000-18ffff 86 32 180000-187fff 87 32 178000-17ffff 88 32 170000-177fff 89 32 168000-16ffff 90 32 160000-167fff 91 32 158000-15ffff 92 32 150000-157fff 93 32 148000-14ffff 94 32 140000-147fff 95 32 138000-13ffff 96 32 130000-137fff 97 32 128000-12ffff 98 32 120000-127fff 99 32 118000-11ffff 100 32 110000-117fff 101 32 108000-10ffff 102 32 100000-107fff 103 32 0f8000-0fffff 104 32 0f0000-0f7fff 105 32 0e8000-0effff 106 32 0e0000-0e7fff 107 32 0d8000-0dffff 108 32 0d0000-0d7fff 109 32 0c8000-0cffff bank b 110 32 0c0000-0c7fff 111 32 0b8000-0bffff 112 32 0b0000-0b7fff 113 32 0a8000-0affff 114 32 0a0000-0a7fff 115 32 098000-09ffff 116 32 090000-097fff 117 32 088000-08ffff 118 32 080000-087fff 119 32 078000-07ffff 120 32 070000-077fff 121 32 068000-06ffff 122 32 060000-067fff 123 32 058000-05ffff 124 32 050000-057fff 125 32 048000-04ffff 126 32 040000-047fff 127 32 038000-03ffff 128 32 030000-037fff 129 32 028000-02ffff 130 32 020000-027fff 131 32 018000-01ffff 132 32 010000-017fff 133 32 008000-00ffff 134 32 000000-007fff
m58cr064c, m58cr064d, m58cr064p, m58cr064q 52/70 table 29. bottom boot block addresses, m58cr064d, m58cr064q bank # size (kword) address range bank b 134 32 3f8000-3fffff 133 32 3f0000-3f7fff 132 32 3e8000-3effff 131 32 3e0000-3e7fff 130 32 3d8000-3dffff 129 32 3d0000-3d7fff 128 32 3c8000-3cffff 127 32 3c0000-3c7fff 126 32 3b8000-3bffff 125 32 3b0000-3b7fff 124 32 3a8000-3affff 123 32 3a0000-3a7fff 122 32 398000-39ffff 121 32 390000-397fff 120 32 388000-38ffff 119 32 380000-387fff 118 32 378000-37ffff 117 32 370000-377fff 116 32 368000-36ffff 115 32 360000-367fff 114 32 358000-35ffff 113 32 350000-357fff 112 32 348000-34ffff 111 32 340000-347fff 110 32 338000-33ffff 109 32 330000-337fff 108 32 328000-32ffff 107 32 320000-327fff 106 32 318000-31ffff 105 32 310000-317fff 104 32 308000-30ffff 103 32 300000-307fff 102 32 2f8000-2fffff 101 32 2f0000-2f7fff 100 32 2e8000-2effff 99 32 2e0000-2e7fff 98 32 2d8000-2dffff 97 32 2d0000-2d7fff 96 32 2c8000-2cffff 95 32 2c0000-2c7fff bank b 94 32 2b8000-2bffff 93 32 2b0000-2b7fff 92 32 2a8000-2affff 91 32 2a0000-2a7fff 90 32 298000-29ffff 89 32 290000-297fff 88 32 288000-28ffff 87 32 280000-287fff 86 32 278000-27ffff 85 32 270000-277fff 84 32 268000-26ffff 83 32 260000-267fff 82 32 258000-25ffff 81 32 250000-257fff 80 32 248000-24ffff 79 32 240000-247fff 78 32 238000-23ffff 77 32 230000-237fff 76 32 228000-22ffff 75 32 220000-227fff 74 32 218000-21ffff 73 32 210000-217fff 72 32 208000-20ffff 71 32 200000-207fff 70 32 1f8000-1fffff 69 32 1f0000-1f7fff 68 32 1e8000-1effff 67 32 1e0000-1e7fff 66 32 1d8000-1dffff 65 32 1d0000-1d7fff 64 32 1c8000-1cffff 63 32 1c0000-1c7fff 62 32 1b8000-1bffff 61 32 1b0000-1b7fff 60 32 1a8000-1affff 59 32 1a0000-1a7fff 58 32 198000-19ffff 57 32 190000-197fff 56 32 188000-18ffff 55 32 180000-187fff
53/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q bank b 54 32 178000-17ffff 53 32 170000-177fff 52 32 168000-16ffff 51 32 160000-167fff 50 32 158000-15ffff 49 32 150000-157fff 48 32 148000-14ffff 47 32 140000-147fff 46 32 138000-13ffff 45 32 130000-137fff 44 32 128000-12ffff 43 32 120000-127fff 42 32 118000-11ffff 41 32 110000-117fff 40 32 108000-10ffff 39 32 100000-107fff bank a 38 32 0f8000-0fffff 37 32 0f0000-0f7fff 36 32 0e8000-0effff 35 32 0e0000-0e7fff 34 32 0d8000-0dffff 33 32 0d0000-0d7fff 32 32 0c8000-0cffff 31 32 0c0000-0c7fff 30 32 0b8000-0bffff 29 32 0b0000-0b7fff 28 32 0a8000-0affff 27 32 0a0000-0a7fff 26 32 098000-09ffff 25 32 090000-097fff 24 32 088000-08ffff 23 32 080000-087fff bank a 22 32 078000-07ffff 21 32 070000-077fff 20 32 068000-06ffff 19 32 060000-067fff 18 32 058000-05ffff 17 32 050000-057fff 16 32 048000-04ffff 15 32 040000-047fff 14 32 038000-03ffff 13 32 030000-037fff 12 32 028000-02ffff 11 32 020000-027fff 10 32 018000-01ffff 9 32 010000-017fff 8 32 008000-00ffff 7 4 007000-007fff 6 4 006000-006fff 5 4 005000-005fff 4 4 004000-004fff 3 4 003000-003fff 2 4 002000-002fff 1 4 001000-001fff 0 4 000000-000fff
m58cr064c, m58cr064d, m58cr064p, m58cr064q 54/70 appendix b. common flash interface the common flash interface is a jedec ap- proved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the read cfi query command is issued the device enters cfi query mode and the data structure is read from the memory. tables 30, 31, 32, 33, 34 and 35 show the addresses used to re- trieve the data. the query data is always present- ed on the lowest order data outputs (dq0-dq7), the other outputs (dq8-dq15) are set to 0. the cfi data structure also contains a security area where a 64 bit unique security number is writ- ten (see figure 5, security block and protection register memory map). this area can be access- ed only in read mode by the final user. it is impos- sible to change the security number after it has been written by st. issue a read array command to return to read mode. table 30. query structure overview note: the flash memory display the cfi data structure when cfi query command is issued. in this table are listed the main sub-se ctions detailed in tables 31, 32, 33, 34 and 35. query data is always presented on the lowest order data outputs. table 31. cfi query identification string offset sub-section name description 00h reserved reserved for algorithm-specific information 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) 80h security code area lock protection register unique device number and user programmable otp offset sub-section name description value 00h 0020h manufacturer code st 01h 88cah 88cbh 8801h 8802h device code (m58cr064c/d/p/q) top bottom 02h reserved reserved 03h reserved reserved 04h-0fh reserved reserved 10h 0051h query unique ascii string "qry" "q" 11h 0052h "r" 12h 0059h "y" 13h 0003h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm 14h 0000h 15h offset = p = 0039h address for primary algorithm extended query table (see table 33) p = 39h 16h 0000h 17h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 18h 0000h 19h value = a = 0000h address for alternate algorithm extended query table na 1ah 0000h
55/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q table 32. cfi query system interface information table 33. device geometry definition offset data description value 1bh 0017h v dd logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 1.7v 1ch 0020h v dd logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 2.0v 1dh 0017h v pp [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 1.7v 1eh 00c0h v pp [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 12v 1fh 0004h typical time-out per single byte/word program = 2 n s 16s 20h 0003h typical time-out for quadruple word program = 2 n s 8s 21h 000ah typical time-out per individual block erase = 2 n ms 1s 22h 0000h typical time-out for full chip erase = 2 n ms na 23h 0003h maximum time-out for word program = 2 n times typical 128s 24h 0004h maximum time-out for quadruple word = 2 n times typical 128s 25h 0002h maximum time-out per individual block erase = 2 n times typical 4s 26h 0000h maximum time-out for chip erase = 2 n times typical na offset word mode data description value 27h 0017h device size = 2 n in number of bytes 8 mbyte 28h 29h 0001h 0000h flash device interface code description x16 async. 2ah 2bh 0003h 0000h maximum number of bytes in multi-byte program or page = 2 n 8 byte 2ch 0002h number of identical sized erase block regions within the device bit 7 to 0 = x = number of erase block regions 2 m58cr064c/p 2dh 2eh 007eh 0000h region 1 information number of identical-size erase blocks = 007eh+1 127 2fh 30h 0000h 0001h region 1 information block size in region 1 = 0100h * 256 byte 64 kbyte 31h 32h 0007h 0000h region 2 information number of identical-size erase blocks = 000eh+1 8 33h 34h 0020h 0000h region 2 information block size in region 2 = 0020h * 256 byte 8 kbyte 35h 38h 0000h reserved for future erase block region information na
m58cr064c, m58cr064d, m58cr064p, m58cr064q 56/70 table 34. primary algorithm-specific extended query table m58cr064d/q 2dh 2eh 0007h 0000h region 1 information number of identical-size erase block = 0007h+1 8 2fh 30h 0020h 0000h region 1 information block size in region 1 = 0020h * 256 byte 8 kbyte 31h 32h 007eh 0000h region 2 information number of identical-size erase block = 007eh+1 127 33h 34h 0000h 0001h region 2 information block size in region 2 = 0100h * 256 byte 64 kbyte 35h 38h 0000h reserved for future erase block region information na offset data description value (p)h = 39h 0050h primary algorithm extended query table unique ascii string pri "p" 0052h "r" 0049h "i" (p+3)h = 3ch 0031h major version number, ascii "1" (p+4)h = 3dh 0030h minor version number, ascii "0" (p+5)h = 3eh 00e6h extended query table contents for primary algorithm. address (p+5)h contains less significant byte. bit 0 chip erase supported (1 = yes, 0 = no) bit 1 erase suspend supported (1 = yes, 0 = no) bit 2 program suspend supported (1 = yes, 0 = no) bit 3 legacy lock/unlock supported (1 = yes, 0 = no) bit 4 queued erase supported (1 = yes, 0 = no) bit 5 instant individual block locking supported (1 = yes, 0 = no) bit 6 protection bits supported (1 = yes, 0 = no) bit 7 page mode read supported (1 = yes, 0 = no) bit 8 synchronous read supported (1 = yes, 0 = no) bit 9 simultaneous operation supported (1 = yes, 0 = no) bit 10 to 31 reserved; undefined bits are 0. if bit 31 is 1 then another 31 bit field of optional features follows at the end of the bit-30 field. no ye s ye s no no ye s ye s ye s ye s ye s 0003h (p+7)h = 40h 0000h (p+8)h = 41h 0000h (p+9)h = 42h 0001h supported functions after suspend read array, read status register and cfi query bit 0 program supported after erase suspend (1 = yes, 0 = no) bit 7 to 1 reserved; undefined bits are 0 ye s (p+a)h = 43h 0003h block protect status defines which bits in the block status register section of the query are implemented. bit 0 block protect status register lock/unlock bit active (1 = yes, 0 = no) bit 1 block lock status register lock-down bit active (1 = yes, 0 = no) bit 15 to 2 reserved for future use; undefined bits are 0 ye s ye s (p+b)h = 44h 0000h (p+c)h = 45h 0018h v dd logic supply optimum program/erase voltage (highest performance) bit 7 to 4hex value in volts bit 3 to 0bcd value in 100 mv 1.8v offset word mode data description value
57/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q table 35. burst read information (p+d)h = 46h 00c0h v pp supply optimum program/erase voltage bit 7 to 4hex value in volts bit 3 to 0bcd value in 100 mv 12v (p+e)h = 47h (p+f)h = 48h (p+10)h = 49h (p+11)h = 4ah (p+12)h = 4bh 0000h reserved offset data description value (p+13)h = 4ch 0003h page-mode read capability bits 0-7 n such that 2 n hex value represents the number of read- page bytes. see offset 28h for device word width to determine page-mode data output width. 8 bytes (p+14)h = 4dh 0003h number of synchronous mode read configuration fields that follow. 3 (p+15)h = 4eh 0001h synchronous mode read capability configuration 1 bit 3-7 reserved bit 0-2 n such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the devices burstable address space. this fields 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data output width. 4 (p+16)h = 4fh 0002h synchronous mode read capability configuration 2 8 (p+17)h = 50h 0007h synchronous mode read capability configuration 3 cont. (p+18)h = 51h 0036h max operating clock frequency (mhz) 54 mhz (p+19)h = 52h 0001h supported handshaking signal (wait pin) bit 0 during synchronous read (1 = yes, 0 = no) bit 1 during asynchronous read (1 = yes, 0 = no) ye s no offset data description value
m58cr064c, m58cr064d, m58cr064p, m58cr064q 58/70 appendix c. flowcharts and pseudo codes figure 20. program flowchart and pseudo code note: 1. status check of sr1 (protected block), sr3 (v pp invalid) and sr4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase controller operations. write 40h or 10h ai06170 start write address & data read status register yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) program_command (addresstoprogram, datatoprogram) {: writetoflash (bank_address, 0x40) ; /*or writetoflash (bank_address, 0x10) ; */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*vpp invalid error */ error_handler ( ) ; yes end yes no sr1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
59/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q figure 21. double word program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase operations. 3. address 1 and address 2 must be consecutive addresses differing only for bit a0. write 30h ai06171 start write address 1 & data 1 (3) read status register yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) yes end yes no sr1 = 0 program to protected block error (1, 2) write address 2 & data 2 (3) double_word_program_command (addresstoprogram1, datatoprogram1, addresstoprogram2, datatoprogram2) { writetoflash (bank_address, 0x30) ; writetoflash (addresstoprogram1, datatoprogram1) ; /*see note (3) */ writetoflash (addresstoprogram2, datatoprogram2) ; /*see note (3) */ /*memory enters read status state after the program command*/ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.b7== 0) ; if (status_register.sr3==1) /*vpp invalid error */ error_handler ( ) ; if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
m58cr064c, m58cr064d, m58cr064p, m58cr064q 60/70 figure 22. quadruple word program flowchart and pseudo code note: 1. status check of sr1 (protected block), sr3 (v pp invalid) and sr4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase operations. 3. address 1 to address 4 must be consecutive addresses differing only for bits a0 and a1. write 55h ai06172 start write address 1 & data 1 (3) read status register yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) yes end yes no sr1 = 0 program to protected block error (1, 2) write address 2 & data 2 (3) quadruple_word_program_command (addresstoprogram1, datatoprogram1, addresstoprogram2, datatoprogram2, addresstoprogram3, datatoprogram3, addresstoprogram4, datatoprogram4) { writetoflash (bank_address, 0x55) ; writetoflash (addresstoprogram1, datatoprogram1) ; /*see note (3) */ writetoflash (addresstoprogram2, datatoprogram2) ; /*see note (3) */ writetoflash (addresstoprogram3, datatoprogram3) ; /*see note (3) */ writetoflash (addresstoprogram4, datatoprogram4) ; /*see note (3) */ /*memory enters read status state after the program command*/ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.b7== 0) ; if (status_register.sr3==1) /*vpp invalid error */ error_handler ( ) ; if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr==1) /*program to protect block error */ error_handler ( ) ; } write address 3 & data 3 (3) write address 4 & data 4 (3)
61/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q figure 23. program suspend & resume flowchart and pseudo code write 70h ai06173 read status register yes no sr7 = 1 yes no sr2 = 1 program continues write d0h read data from another address start write b0h program complete write ffh read data program_suspend_command ( ) { writetoflash (any_address, 0xb0) ; writetoflash (bank_address, 0x70) ; /* read status register to check if program has already completed */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr2==0) /*program completed */ { writetoflash (bank_address, 0xff) ; read_data ( ) ; /*read data from another block*/ /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (bank_address, 0xff) ; read_data ( ); /*read data from another address*/ writetoflash (any_address, 0xd0) ; /*write 0xd0 to resume program*/ } } write ffh
m58cr064c, m58cr064d, m58cr064p, m58cr064q 62/70 figure 24. block erase flowchart and pseudo code note: if an error is found, the status register must be cleared before further program/erase operations. write 20h ai06174 start write block address & d0h read status register yes no sr7 = 1 yes no sr3 = 0 yes sr4, sr5 = 1 v pp invalid error (1) command sequence error (1) no no sr5 = 0 erase error (1) end yes no sr1 = 0 erase to protected block error (1) yes erase_command ( blocktoerase ) { writetoflash (bank_address, 0x20) ; writetoflash (blocktoerase, 0xd0) ; /* only a12-a20 are significannt */ /* memory enters read status state after the erase command */ } while (status_register.sr7== 0) ; do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ if (status_register.sr3==1) /*vpp invalid error */ error_handler ( ) ; if ( (status_register.sr4==1) && (status_register.sr5==1) ) /* command sequence error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; if ( (status_register.sr5==1) ) /* erase error */ error_handler ( ) ; }
63/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q figure 25. erase suspend & resume flowchart and pseudo code write 70h ai06175 read status register yes no sr7 = 1 yes no sr6 = 1 erase continues write d0h read data from another block or program/protection program or block protect/unprotect/lock start write b0h erase complete write ffh read data write ffh erase_suspend_command ( ) { writetoflash (bank_address, 0xb0) ; writetoflash (bank_address, 0x70) ; /* read status register to check if erase has already completed */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr6==0) /*erase completed */ { writetoflash (bank_address, 0xff) ; read_data ( ) ; /*read data from another block*/ /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (bank_address, 0xff) ; read_program_data ( ); /*read or program data from another address*/ writetoflash (bank_address, 0xd0) ; /*write 0xd0 to resume erase*/ } }
m58cr064c, m58cr064d, m58cr064p, m58cr064q 64/70 figure 26. locking operations flowchart and pseudo code write 01h, d0h or 2fh ai06176 read block lock states yes no locking change confirmed? start write 60h locking_operation_command (address, lock_operation) { writetoflash (bank_address, 0x60) ; /*configuration setup*/ if (readflash (address) ! = locking_state_expected) error_handler () ; /*check the locking state (see read block signature table )*/ writetoflash (bank_address, 0xff) ; /*reset to read array mode*/ } write ffh write 90h end if (lock_operation==lock) /*to protect the block*/ writetoflash (address, 0x01) ; else if (lock_operation==unlock) /*to unprotect the block*/ writetoflash (address, 0xd0) ; else if (lock_operation==lock-down) /*to lock the block*/ writetoflash (address, 0x2f) ; writetoflash (bank_address, 0x90) ;
65/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q figure 27. protection register program flowchart and pseudo code note: 1. status check of sr1 (protected block), sr3 (v pp invalid) and sr4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase controller operations. write c0h ai06177 start write address & data read status register yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) protection_register_program_command (addresstoprogram, datatoprogram) {: writetoflash (bank_address, 0xc0) ; do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*vpp invalid error */ error_handler ( ) ; yes end yes no sr1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
m58cr064c, m58cr064d, m58cr064p, m58cr064q 66/70 appendix d. command interface state tables table 36. command interface states - lock table note: ps = program suspend, es = erase suspend. current state of other bank current state of the current bank command input to the current bank (and next state of the current bank) mode state others read array (ffh) erase confirm p/e resume unlock confirm (d0h) read status register (70h) clear status register (50h) read electronic signature (90h) read cfi query (98h) block lock unlock lock-down setup set cr setup (60h) block lock confirm (01h) block lock- down confirm (2fh) set cr confirm (03h) any state read array see modi fy table read array read array read status register read array read el ect. si gn. read cfi block lock, unlock, lock-down, set cr setup read array read array read array cfi electronic signature status any state lock unlock lock-down cr setup block lock unlock lock-down error, set cr error bl ock lock unlock lock-down error, set cr error block lock unlock lock-down bl ock block lock unlock lock-down error, set cr error block lock unlock lock-down error, set cr error block lock unl ock lock-down error, set cr error block lock unlock lock-down error, set cr error block lock unlock lock-down error, set cr error block lock unlock lock-down block block lock unlock lock-down bl ock set cr error see modi fy table read array read array read status register read array read el ect. si gn. read cfi block lock unlock lock-down setup, set cr set up read array read array read array lock unlock lock-down bl ock set cr any state protection register done see modi fy table read array read array read status register read array read el ect. si gn. read cfi block lock unlock lock-down setup, set cr set up read array read array read array any state program- double/ quadruple program done see modi fy table read array read array read status register read array read el ect. si gn. read cfi block lock unlock lock-down setup, set cr set up read array read array read array setup program suspend read array, cfi, el ect. sign., status see modi fy table ps read array program (busy) ps read status register ps read array ps read el ect. si gn. ps read cfi ps read array ps read array ps read array ps read array idle erase suspend idle bl ock/ bank erase setup erase error erase error erase (busy) erase error erase error erase error erase error erase error erase error erase error erase error any state error see modi fy table read array read array read status register read array read el ect. si gn. read cfi block lock unlock lock-down setup, set cr set up read array read array read array done setup erase suspend read array, cfi, el ect. sign., status see modi fy table es read array erase (busy) es read status register es read array es read el ect. si gn. es read cfi block lock unlock lock-down setup, set cr set up es read array es read array es read array busy es read array idle erase (busy) program suspend es read array
67/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q table 37. command interface states - modify table note: ps = program suspend, es = erase suspend. current state of the other bank current state of the current bank command input to the current bank (and next state of the current bank) mode state others program setup (10h/40h) block erase setup (20h) program-erase suspend (b0h) protection register program setup (c0h) double/ quadruple program setup (30h/55h) bank erase setup (80h) setup read array, cfi, electronic signature, status register see lock table read array read array read array read array read array read array busy idle program setup block erase setup protecti on register setup double/ quadruple program setup bank erase setup erase suspend read array read array read array program suspend read array read array setup lock unlock lock-down cr error, lock unlock lock-down block, set cr see lock table read array read array read array read array read array read array busy idle program setup block erase setup protecti on register setup double/ quadruple program setup bank erase setup erase suspend read array read array read array program suspend read array read array idle protection regi st er setup protection register (busy) protection register (busy) protection register (busy) protection register (busy) protecti on register (busy) protection register (busy) protection register (busy) setup busy busy done see lock table read array read array read array read array read array read array idle program setup block erase setup protecti on register setup double/ quadruple program setup bank erase setup erase suspend read array read array read array program suspend read array read array any state program double/ quadruple word program setup program (busy) program (busy) program (busy) program (busy) program (busy) program (busy) program (busy) idle busy ps read status register setup done see lock table read array read array read array read array read array read array busy idle program setup block erase setup protecti on register setup double/ quadruple program setup bank erase setup erase suspend read array read array read array program suspend read array read array setup program suspend read array, cfi, elect. sign., status regi st er see lock table ps read array ps read array ps read array ps read array ps read array ps read array idle erase suspend idle block/ bank erase setup see lock table erase error erase error erase error erase error erase error erase error busy erase (busy) erase (busy) erase (busy) es read status register erase (busy) erase (busy) erase (busy) setup erase suspend read array, cfi, elect. sign., status regi st er see lock table es read array es read array es read array es read array es read array es read array busy idl e program setup double/ quadruple program setup program suspend es read array es read array
m58cr064c, m58cr064d, m58cr064p, m58cr064q 68/70 revision history table 38. document revision history date version revision details november 2000 -01 first issue 12/20/00 -02 protection/security clarification memory map diagram clarification (figure 4) single synchronous read clarification (figure 6) identifier codes clarification (table 6) x-latency configuration clarification cfi query identification string change (table 31) synchronous burst read waveforms change (figure 12) reset ac characteristics clarification (table 24) program time clarification (table ) 1/08/01 -03 reset ac characteristics clarification (table 24) reset ac waveforms diagram change (figure 1) 3/02/01 -04 document type: from target specification to product preview read status register clarification read electronic signature clarification protection register program clarification write configuration register clarification wait configuration sequence change (figure 7) cfi query system interface clarification (table 32) cfi device geometry change (table 33) asynchronous read ac waveforms change (figure 10) page read ac waveforms added (figure 11) write ac waveforms w contr. and e contr. change (figure 14, 15) reset and power-up ac characteristics and waveform change (table 24, figure 1) tfbga package mechanical data and outline added (table 25, figure 17) 4/05/01 -05 tfbga connections change x-latency configuration sequence change reset and power-up ac characteristics clarification v ddq clarification 23-jul-2001 -06 complete rewrite and restructure 23-oct-2001 -07 85ns speed class added, document classified as preliminary data 15-mar-2002 -08 part numbers m58cr064p/q added. cfi information clarified: table 31,data modified at offset 13h. table 32, data modified at offsets 20h, 23h, 24h and 25h. table 35, offset addresses modified. dc characteristics table modified, program, erase times and program, erase endurance cycles table modified. 23-may-2002 -09 document changed to new structure 27-aug-2002 9.1 revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot. (revision version 09 equals 9.0). document status changed from preliminary data to datasheet. minimum v dd and v ddq supply voltages for 85ns speed class changed to 1.8v in table16, operating and ac measurement conditions.
69/70 m58cr064c, m58cr064d, m58cr064p, m58cr064q 24-feb-2003 9.2 revision history moved to end of document. 90ns speed class added. bank erase command moved to factory program commands section. bank erase cycles limited to 100 per block. wait signal modified in figure 7, wait configuration example. wait behavior modified. burst sequence in wrapped configuration and burst sequence start specified in synchronous burst read mode paragraph. erase replaced by block erase in tables 11 and 12, dual operations allowed in other bank and in same bank, respectively. latch signal corrected in figure 11, asynchronous page read ac waveforms. daisy chain added. 06-jun-2003 9.3 v dd and v ddq minimum values changed for 90ns speed class in table 16, operating and ac measurement conditions. minor text changes. date version revision details
m58cr064c, m58cr064d, m58cr064p, m58cr064q 70/70 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unite d states. www.st.com

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